Beetle - a readout chip for LHCb
 |
 |
Content
BeetleSR1.0
BeetleSR1.0 is a test chip submitted in May 2001. It integrates two types of I2C-interfaces, a standard and an SEU robust one using triple redundant logic, and two memory blocks consisting of 34 8-bit registers each. The layout of the chip with the corresponding floor plan is shown below. The registers forming the memory blocks use standard flip-flops without any redundancy.
Each of the two interface circuits can be accessed via separate I2C-ports. Nine parity bits per register block are generated, where 8 of them are the parity of 4 registers (Parity[7:0]) and 1 the parity of 2 (Parity[8]).
Letzte Änderung: 10 Feb 2003