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Large-scale neuromorphic hardware systems typically bear the trade-off between detail level and required chip resources. Especially when implementing spike-timing-dependent plasticity, reduction in resources leads to limitations as compared to floating point precision. By design, a natural modification that saves resources would be reducing synaptic weight resolution. The FACETS wafer-scale hardware system, a pioneering neuromorphic device that implements a large amount of synapses, will offer a 4-bit resolution of synaptic weights. In this study, we give an estimate for the impact of synaptic weight discretization on different levels, ranging from random walks of individual weights to computer simulations of spiking neural networks. Within the scope of network benchmarks that have been used in this study, we conclude that 4-bit is indeed a sufficient weight resolution. Our results indicate that increasing the resolution may not even be useful in light of further restrictions of customized mixed-signal synapses. In addition, variations due to production imperfections are investigated using the already existing FACETS chip-based hardware system, and are shown to be uncritical in the context of the presented study. Our results represent a general framework for setting up and configuring hardware-constrained synapses. We suggest how weight discretization could be in addition considered for other backends dedicated to large scale simulations. Thus, our proposition of a good hardware verification practice may rise synergy effects between hardware developers and neuroscientists.