| Jahr | 2015 |
| Autor(en) | K. Briggl, H. Chen, W. Shen and H.C. Schultz-Coulon |
| Titel | Low power Analog Digital Converter for a silicon photomultiplier readout ASIC |
| KIP-Nummer | HD-KIP 15-105 |
| KIP-Gruppe(n) | F11 |
| Dokumentart | Paper |
| Quelle | JINST 10 2015 C04041 |
| doi | doi:10.1088/1748-0221/10/04/C04041 |
| Abstract (de) | We present an ADC designed in the UMC 0.18um CMOS technology. It will be used in the SiPM analog front-end ``KLauS" developed for the analog hadronic calorimeter at ILD. Key parameter in this application is an extremely low power consumption of the front-end electronics. For quantization of the energy depositions, a 10-bit ADC resolution is required. For calibration purposes, a 12-bit quantization is used. A successive approximation register split capacitor array structure is chosen to minimize the DC power consumption. A peak sensing block is used to minimize the required sampling rate. We present design details and simulation results of the ADC, as well as the peak sensing track & hold circuit. |
| bibtex | @article{174802211004C04041,
author = {K. Briggl and H. Chen and W. Shen and H.C. Schultz-Coulon},
title = {Low power Analog Digital Converter for a silicon photomultiplier readout ASIC},
journal = {Journal of Instrumentation},
year = {2015},
volume = {10},
number = {04},
pages = {C04041},
url = {http://stacks.iop.org/1748-0221/10/i=04/a=C04041}
} |
| URL | IOP Link |
