KIP-Veröffentlichungen

We present the design and measurement of a continuous-time, accelerated, reconfigurable Leaky Integrate and Fire (LIF) neuron model emulated in 65-nm CMOS technology. The neuron circuit is designed as a sub-circuit of our highly integrated neuromorphic prototype chip, the “HICANN-DLS”. The design is geared towards testability and debug features, as well as area and power efficiency. Each neuron in the array integrates current from a multitude of input synapses onto an RC integrator within the synaptic input sub-circuit, where a variable resistor tunes the synaptic time constant. Linear transconductors convert voltage into an equivalent current as well as modeling the leak term, while a pulse generator circuit evokes a digital spike event. Our measurements show that the neuron successfully integrates input synaptic events ranging from a few nA to greater than 10 µA and tunes a wide range of tunable synaptic and membrane time constants. A higher membrane dynamic range of up to 1100 mV, and longer refractory times can be achieved, operating 1000 times faster than biological real-time. The design of the neuron simplifies calibration and reduces the mismatch, as multiple die measurements indicate. We demonstrate a one-to-one correspondence to software simulation for a typical computational model neuron. Due to the wide tunable range, the neuron is to be our general-purpose element of our second generation flexible neuromorphic platform for a variety of computational models.