Style guide for ASIC-designers

Motivation

This introduces the need for agreements e. g. on signal and design module names, a uniform way of documentation, even for a defined style how to draw schematics. All this mostly is no definite need but it helps maintaining a large project tremendously.

General

Purpose and author

• How to contact the author. Write down your name and address, maybe even your mail address so that people can contact you when they have questions
• When was the file created, which changes were made when and by whom
• What does the document show in principle

Name conventions

• Use english names
• Only use alphabetical characters or numeric digits. Don´t use any special characters like _, $, "german Umlaute" or something else. They could have a special meaning in one of the many tools Cadence consists of.
• Design/module names start with an uppercase letter (e. g. Ctr4udar for a counter module)
• Pins of such a module start with an uppercase letter (e. g. Ctr4udar(Clk, ...))
• Names which are only internal to a design are all start with a lowercase letter
• Active low binary signals are indicated by the all-lowercase prefix not
• Bus indices always count from n-1 downto 0 (for a bus of n bits width)

Design organisation

• Organise your design hierachically
• Keep the names of global signals (e. g. system wide clocks, system reset signals a. s. o.) throughout the hierachy (that simplifies finding them later in the layout)

Verilog

• Each Verilog module of name name must be stored in a separate file of name name.v
• After the module declaration there must be a header containing information about the module and the author as described in topic "General".

The header must be placed after the module declaration to make sure that the Cadence Verilog import process does not purge it (it only keeps information within modules).
• Any parameter statements must follow the header
• Any define statements must follow the parameter statements
• The input /output statements must follow with documentation

module CtrNudar(Clk, notReset, UpNotDown, Out);
//
// N bit positive edge triggered binary up/down counter with asynchronous reset.
// Author            : Martin Feuerstack-Raible
// Edition history   :
// 98/04/20    mfr    Created
//
parameter    N = 4;        // Width of the counter. Default is 4 bit

input        Clk;          // Counter clock. States changes at the positive edge
input        notReset;     // Asynchronous active low reset. Set <Out> to 0 (zero)
input        UpNotDown;    // Counting direction: 1 = count up, 0 = count down
output [N - 1 : 0] Out;    // Binary output

Schematic

• Any manually created schematic must be placed within a frame (i. e. US_8ths) which contains above mentioned general information about author and purpose of the design.

Layout

• PCells must be flattened in the final design (otherwise the design might not be portable to the next Cadence version)

Documentation

Project specific conventions

• At the most early state of the project possible agree on a power supply concept, i. e. define the names for the different power supplies the design needs. For example use only the following signals from the analogLib:
• vdd for digital supply
• vdda for analog supply
• gnd for substrate contact
Other conventions may be necessary for other projects.

Process specific conventions

   AMS processes

Last changes: 98/02/27 by Martin Feuerstack-Raible