Mini@sic Facets_FG submitted to verify analogue submodules for the HICANN Chip.
On may 20th the Mini@sic Facets_FG has been submitted. Two submodules for the later HICANN chip are to be verified by this asic: The first is the final version of the Floating Gate array including operational amplifiers for global parameters in the first row. The second module are the receivers for the HICANN high speed serial links reaching transfere rates up to 2 GBit/s.
Return date from fab is expected to be august. The chip will be onboard bonded in the local ASIC lab and testet via the evaluation board used for FACETS prototyping.
Last update of this page: 2008-05-23 by Sebastian Millner
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