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Projects
FACETS (2006–2010) & FACETS-ITN (2009–2013)
Neuromorphic Hardware
Single Chip System
Isochronous Multi-Chip Operation
The single-chip framework of the Electronic Vision(s) group requires different data types to be transported with individual demands for quality of service (QoS): Inter-neuron data models fixed axonal connections of biological neurons and thus relies on a deterministic timing. Transport requests for high-level configuration data arise on-demand during experiments and require a packet-based approach. The interconnection of the distributed components uses a dedicated network protocol, which has been developed and optimized especially for this application. It provides two different service classes via the same physical medium:
The online part of the network protocol is implemented completely within the programmable logic of the field-programmable gate arrays (FPGAs) on the network modules. The network protocol uses a novel switch type that performs the traffic class integration. The switch architecture combines techniques from circuit switching and packet switching to best support both traffic classes. It uses buffer-less forwarding of isochronous data to minimize its end-to-end jitter, which is nearly independent of the number of network hops. At the same time, best-effort data is forwarded as in packet-switched networks. The modular design of the switch makes it possible to use common scheduling algorithms for this task.
