Appendix: List of Known Problems

 

1.

Multi-event buffer non functional (1);  
due to unfavorable routing of Sclk the chip has to be reset after each trigger. The employment of Helix128-2.0 should be restricted to laboratory evaluation.

2.

Multi-event buffer (2);  
at certain well defined conditions a trigger can halt the chip.

3.

VcompRef adjustment;  
VcompRef is the dicriminator reference voltage of the comparators. It runs from -2V to +2V in 128 steps, giving a resolution of $\approx$ 31mV. Compared to the response to a signal of 1MIP$_{\rm Si}$ (24.000 electrons) of $\approx$ 50mV, this is much to coarse.

4.

Sclk and Rclk;  
Sclk and Rclk are unipolar (nondifferential) signals which may cause excess noise on the chip, especially at fast Rclk timings.

5.

SerClk and Rclk;  
Rclk must run faster than SerClk otherwise data might be lost.

6.

DataValid, AnalogOut and AnalogOutDummy; 
AnalogOut and AnalogOutDummy jitter with respect to DataValid. The jitter can be up to 4 Rclk cycles, but is the same for all chip that have their notReset released at the same time.

7.

Offset of AnalogOut and AnalogOutDummy; 
due to unfavorable voltage level transitions in the pipeline readout amplifier, AnalogOut and AnalogOutDummy have a Sclk-dependent offset, which limits the dynamic range.

8.

Crosstalk of switching comparator to all channels;  
feedback via the open-collector discriminator outputs at the chip's bottom side to the amplifier inputs is suspected.

9.

Pairwise crosstalk between channels (2n,2n+1) of approx. 8 %;  
even if the pattern follows an asymmetry in the pipeline, the origin is not yet clear.

10.

Radiation softness of Pipeline amplifier;  The functionality of the Pipeamp suffers from very low radiation doeses. It is believed that this problem is related with problem 7.

11.

Light sensitivity of the pipeline amplfier;  The pipeline read ot amplifier suffers from extreme light sensitivity. Exposure to light drives the amplifier into saturation when the chip is not read out and the reset period before each read out cycle is not long enough to recover the amplifier from this state. This problem mainly occurs at low trigger rates (less than 100Hz). Higher trigger rates keep the amplifier operable.

12.

Startup of the internal bias current source;  Some chips do not become operation because the internal current source does not start.

13.

Oscillation of the internal current source;  The internal current source shows oscillation, which increases common mode noise and limits the comparator threshold. The nearly sine-shaped oscillation of approx. 10MHz can be eliminated completely at most chips by blocking the reference resistor connected to the Rref pad. However, then some chips still show a saw-tooth like oscillation of some 100kHz.