Important note

This manual describes different versions of the second generation of the Helix readout-chip; the chips developed so far differ in some details, especially concerning pad layout and electrical specification of some control signals. The Helix128-2 (sometimes also called Helix128-2.0) chip is the first in this line; Helix128-2.1 emerged from it by a metal/poly mask redesign.

Helix128-2.2 is an improved version making use of a modified pipeline readout amplifier; it is equipped with LVDS line receivers for some control lines and with a pad layout that will make it compatible with a fail safe token scheme which will be implemented in future. Finally, Helix128-2.3 is a derivation of Helix128-2.2 with yet another pipeline readout amplifier.

The name Helix128-2 is used throughout this manual when describing features that are common for all versions of the chip.

The Helix128-3.0 includes some remaining bug fixes and in addition has implemented a failsafe token mechanism, which enhances reliability in systems with large daisy chains. Only changes applied to this chip with respect to its predecessors are discussed here. The chip will be completely described in its own manual.