Analog Signal Processing Architecture

Helix128-2 is an analog readout chip for silicon microstrip detectors and microstrip gaseous chambers specially suited to the needs of the HERA-B experiment [1]. Major electrical specifications are a 10MHz sampling clock frequency (i. e. the bunch crossing frequency) implying a shaper peaking time in the 50 ns regime, a storage time depth of about 10$\mu$s to comply with the first level trigger latency, the ability to store up to eight events to equalize statistical trigger fluctuations and the complete deadtimeless readout of the detectors in 10$\mu$s due to the mean second level trigger rate of 100kHz. Further demands are lowest possible total system noise and a moderate radiation tolerance of $\leq$2kGy.

To cope with the tremendous amount of detector channels 128 channels are integrated per chip with 41.4$\mu$m pitch (which yields in a 50$\mu$m overall pitch) of input pads as imposed by the silicon strip detector pitch.