Overview

Helix128-2 contains 128 channels (see fig. 1), each consisting of

• a low noise charge sensitive preamplifier for signals of both polarities. It is implemented as a folded cascode amplifier circuit with a 342 fF feedback capacitor yielding a gain of 11.2 mV/MIP$_{\rm Si}$ (1 MIP$_{\rm Si}$=24000 electrons).
• a CR-RC shaper forming a semigaussian pulse with a peak time of 50$\ldots$ 70ns.
• a buffer amplifier driving the internal pipeline write line and the pipeline cell.
• a comparator circuit indicating hit channels, the output of four neighbouring channels being ORed and brought offchip via open drain outputs.
• an analog pipeline consisting of 128+8+5 capacitors resulting in a maximum latency of 128 events and a multievent buffer capable of storing up to eight triggered events (time slots)
• a switched charge sensitive pipeline readout amplifier.

A cascaded 128+8+1 channel multiplexer and a current output buffer are provided for the fast serial readout of the analog data and the 8 bit pipeline column number.

  

Figure 1: Schematic diagram of Helix128-2

The operation points of all Helix128-2 amplifier stages can be adjusted via programming of corresponding DAC registers. We will outline radiation compensation strategies which ensure proper operation up to the demanded dose of HERA-B. Further explanation of the suggested strategies can be found in [5] and [6].