The pipeline

The frontend outputs are stored in a sample&hold capacitor array of $129\times(128+8+5)$ cells. Each cell capacitor (850 fF) is connected by a read switch to the read line (frontend output), and by a write switch to the write line leading to the pipeline readout amplifier (``pipeamp'') (fig. 1). The switches are controlled by the pipeline logic which is explained in more detail in section 4.1.

The charge stored per MIP$_{\rm Si}$ is $\approx$ 260.000 electrons implying a charge gain of 11, so that the noise requirements on the pipeamp are relatively relaxed.