The pipeline and readout control logic

  The pipeline control logic (see fig. 1) receives incoming triggers via the interface circuit and tags the corresponding columns of the capacitor storage array such that they are not overwritten by new data before they are read out.

A write pointer scans over the pipeline columns incremented by the sampling clock Sclk which can be either internally generated from the Rclk or taken from the Sclk pad (refer to section 4.4). After notReset is set to +2 V, the pointer starts its walk at column 0, the one nearest to the frontend, wrapping around at column number 140 = 128 + 8 + 5 - 1. Sampling the output of the preamplifier/shaper to the storage capacitor is enabled during the high period of Sclk, the falling edge determining the held frontend output value.

With the latency specified by the content of the Latency register the trigger pointer follows the write pointer. When a trigger occurs (indicated by a high TrigIn   signal at the rising edge of Sclk, see fig. 11), the column number which is currently pointed at by the trigger pointer is stored into a FIFO and marked to be read out. The FIFO has a storage capacity of eight numbers.

  

Figure 11: Sampling of the TrigIn-signal occurs at the rising edge of Sclk; if more than 8 triggers are given in fast sequence, the derandomizing buffer flows over signalling ``FifoFull''

The ``oldest'' number within the FIFO is loaded into the read pointer which adresses the column of the storage capacitor array to be loaded into the readout multiplexer. Loading the multiplexer is a multi-stage process: it takes 2 Sclk cycles to reset the readout line and the pipeamp, followed by 1 Sclk cycle break and another 2 Sclk cycles to read the data with the pipeamp until its output is stored by the readout multiplexer. After this period the multiplexer is ready to transmit data.

The condition for the multiplexer to start transmission once it has loaded data is given by a high TransmitEnable, a high MultiplexerEnable and the presence of a token (as explained in section 4.6).

After transmission of data the chip immediately starts loading data from the next tagged column into the multiplexer. In parallel, the chip watches its ReturnTokenIn line. When this is high during a falling edge of Rclk, the previous pipeline column is untagged thus being available for writing again. Thus, since all chips in a daisy chain share the ReturnToken line, the synchronicity of pipeline operation is maintained even in daisy chain operation.