The multiplexer

  

Figure 7: Cascaded 128+8+1 channel multiplexer

The multiplexer (fig. 7) has been implemented using a cascaded architecture, i. e. in the first stage four 34 channel multiplexers operate at a fourth of the Rclk rate with a second stage at full Rclk speed. This approach would lead to a reordering of the channel numbers. Thus, to equalize this effect a permutation fan through has been implemented so that the channels arrive at the output in their geometrical order. The multiplexer first stage consists of a buffered sample&hold circuit with the drive strength controlled by Isf.

In case of radiation damage the following strategy is recommended:

• Isf should be kept constant; if the buffer becomes too slow by a decrease of g_m, (this can be observed e. g. by changing pulse heights at different Rclk frequencies) Isf can be increased.

As can be seen from fig. 7 8 bits denominating the pipeline column the current event has been stored in are ``weaven'' into the multiplexer, appearing as trailer in the analog output (fig. 9).