Springe direkt zu Talks vom Jahr

2019 2018 2017 2016 2015 2014 2013 2012 2011 2010

Seminars 2019

27.11.2019

• Capmem bugfix and MADC Characterization - Khaleelulla Khan (capmem slides|madc slides|madc chart and registers)

20.11.2019

• The state of the neuron - Sebastian Billaudelle (Slides)
• Simulated Calibration and Testing of Neurons on HX - Philipp Dauer (Slides)

06.11.2019

• Proposal and Design of Back Illuminated 3D Silicon Photomultiplier - Dr. Wei Shen (Slides)

23.10.2019

• PCI-Express on Stratix10 Handson - Christian Pehle

09.10.2019

• Near-term packaging options for Multi-Hicann-X operation - Dr. Johannes Schemmel

25.09.2019

• 25. ASIC-Labor Jubiläum

07.08.2019

• BrainScaleS Extoll Testing and inter-FPGA Spike-Communication - Tobias Thommes (Slides)

26.06.2019

• HICANN-X Analog Results - Sebastian Billaudelle (Slides)

29.05.2019

• On-chip calibration on HICANN-DLS - Aron Leibfried (Slides)

08.05.2019

• Vendor-independent FPGA synthesis with Synplify - Dr. Mitja Kleider (Slides)

03.04.2019

• Waiting for HICANN-X: Building an FPGA design to interface with an asynchronous co-Processor - Vitali Karasenko (Slides)

27.02.2019

• The MuPix8 - a large scale HV-MAPS prototype - Jan Hammerich (Slides)

20.02.2019

• General Design Flow in GF FDX 22nm - Tobias Markus (Slides)

23.01.2019

• Presentation: Semi-automatic flip-chip bonder - Herr Vogel
• Fineplacer user experience - Dr. Christian Kreidl (Slides)

Seminars 2018

12.12.2018

• Status Update - 60GHz Transmitter - Hans Kristian Soltveit
• Sonnet Hands-On - Markus Dorn (GIT)

11.07.2018

• TCAD simulation on the MuPix sensor prototypes - Annie Meneses @HighRR-Seminar (Slides)

04.07.2018

• Scaling-Up BrainScaleS next generation - Dr. Johannes Schemmel (Slides)

16.05.2018

• HICANN-X - Tapeout Resume - Dr. Andreas Grübl (Slides)

02.05.2018

• 60GHz Transceiver Development - Hans Kristian Soltveit

25.04.2018

• Mu3e Readout based on HV-CMOS and real time processing - Sebastian Dittmeier (Slides)

14.03.2018

• HICANN-X L2: A communication protocol using generic units - Vitali Karasenko (Slides)

07.03.2018

• Walk through schematics for the Analog readout chain in HICANN-X - Gerd Kiene

07.02.2018

• Routing of neural events in HICANN-X -- a short introduction - Dr. Johannes Schemmel (Slides)

31.01.2018

• Changes to the neuromorphic neuron circuit for HICANN-X - Sebastian Billaudelle (Slides)

Seminars 2017

13.12.2017

• PACIFICr5 test results - Dr. Albert Comerma (Slides)

15.11.2017

• Extended analog readout chain for the HICANN-X - Gerd Kiene (Slides)

08.11.2017

• MuPix8 - First Measurements and Features - Heiko Augustin (Slides)

20.09.2017

• UVM Verification for HICANN-DLS - Dr. Andreas Hartel (URLs)

09.08.2017

• A temperature-stable exponential current generator - brainstorming - Sebastian Billaudelle

19.07.2017

• CADC in silico - Korbinian Schreiber (Slides)

05.07.2017

• Mixed-Signal Neuron and Readout Circuits for a Neuromorphic System - Gerd Kiene (Slides)
• Synaptic depressin and facilitation for HICANN-DLS - Sebastian Billaudelle (Slides)

21.06.2017

• KlauS4 characterization and operation at DESY test-beam - Konrad Briggl (Slides)

24.05.2017

• The Play Pen -- HC14 Spike Interface - Korbinian Schreiber

10.05.2017

• BrainScales 2: A Novel Architecture for Analog Accelerated Neuromorphic Computing Including Hybrid Plasticity - Dr. Johannes Schemmel (Slides)

03.05.2017

• New testboard for HICANN-DLS - Korbinian Schreiber

26.04.2017

• Impressions and pictures from Yxlon visit - Ralf Achenbach (Owncloud PW can be request from me)

12.04.2017

• Extoll Tourmalet Cards @HBP (Extoll is a spin-off from ZITI-CAG) - Dr. Andreas Grübl, Dr. Eric Müller

05.04.2017

• [Promotion] Microfocus/Nanofocus X-ray Inspection System - Rothmeier SMT Solutions

29.03.2017

• Novel And Exotic Packaging And Test Equipment - Ralf Achenbach (Slides)

22.03.2017

• Depleted Monolithic Active Pixel Sensors - Heiko Augustin @HighRR-Seminar (Slides)

08.03.2017

• Bumping and flip chip of ASICs - Dr. Christian Kreidl @HighRR-Seminar (Slides)

15.02.2017

• A fully differential analog neuron study - Gerd Kiene (Slides)
• Render GDS into 3d - Gerd Kiene (GDS3D based on gds2pov)

01.02.2017

• Self-biased PLL design and noise analysis - David Schimansky (Slides)

18.01.2017

• Updates on the KLauS ASIC for ILC - Zhenxiong Yuan (Slides)

11.01.2017

• New memory architecture for upcoming HICANN-DLS-SR - Christian Pehle (Slides)

Seminars 2016

07.12.2016

• First impressions from KLauS4 ASIC - Konrad Briggl (Slides)

23.11.2016

• Switched-capacitor based ADC frontend - Gerd Kiene (Slides)

09.11.2016

• Overview and power design for 48 channel 32 Msps digitizer board - Joscha Ilmberger (Slides)

02.11.2016

• Gigabit Data Transmission Test for the ATLAS Upgrade - Dr. Tobias Harion (Slides)

07.09.2016

• Porting a RISC-V processor to SystemVerilog - Christian Pehle

24.08.2016

• Automated design exploration using VHDL testbenches and Modelsim - Vitali Karasenko (Slides)
• A random number generator for HICANN-DLS - Christian Pehle

10.08.2016

• Wiring and connectivity with Cadence Virtuoso - Dr. Johannes Schemmel

20.07.2016

• Synaptic depression and facilitation for HICANN-DLS - Sebastian Billaudelle (Slides)

13.07.2016

• Digital neuron backend for HICANN-DLS - Gerd Kiene (Slides)

06.07.2016

• CADC for HICANN-DLS - Korbinian Schreiber (Slides)

08.06.2016

• SC analog readout chain for HICANN-DLS - Gerd Kiene (Slides)

11.05.2016

• Submission Readiness Review: KLauS 4 - Konrad Briggl

14.04.2016

• Hands-On: Automated simulation and analysis using Python - Sebastian Billaudelle (URL)

30.03.2016

• Overview 10bit SAR ADC in TSMC 65nm - Korbinian Schreiber

23.03.2016

• Design and Measurement of HICANN-DLS-2 Neuron - Syed Ahmed Aamir (Slides)

17.02.2016

• PACIFICr3 Test Results - Dr. Albert Comerma (Slides)

27.01.2016

• Well Proximity Effects in TSMC 65nm - Dr. Johannes Schemmel (Slides)

20.01.2016

• KLauS 3 characteristics - Konrad Briggl (Slides)

13.01.2016

• In-house wafertest in our cleanroom - Dr. Andreas Grübl (Slides)

Seminars 2015

03.12.2015

• Synopsys TCAD device simulation and avalanche generation - Dr. Wei Shen (Slides)

21.10.2015

• Basic UVM (Universal Verification Methodology) - Christian Pehle

07.10.2015

• The Good, the Bad and the Ugly: Hardware verification methodology - Vitali Karasenko (Slides) (Summer School Files)

16.09.2015

• TSMC 65nm Analog and Mixed-Signal training workshop highlights - Dr. Matthias Hock

19.08.015

• First results/measurements on KLauS ADC - Konrad Briggl (Slides)

14.06.2015

• PCB-Poweranalysis with Allegro/PowerDC - Joscha Ilmberger (Pictures)

17.06.2015

• Overview talk about PACIFIC asic - Dr. Albert Comerma (Slides)

10.06.2015

• Good to know stuff about Calibre LVS - Dr. Matthias Hock

20.05.2015

• Common pitfalls in full custom ADC design - Dr. Johannes Schemmel & Dr. Simon Friedmann

06.05.2015

• KLauS 3 - mini@sic in UMC 180nm - Konrad Briggl (Slides)

29.04.2015

• HICANN V4 - Digital power improvements - Dr. Andreas Grübl

22.4.2015

• Wrap Up - HICANN V4 submission - Dr. Johannes Schemmel

25.2.2015

• Submission Readiness Review: KLauS-ADC - Dr. Wei Shen

18.2.2015

• Study of MUPIX6 Sensor Performance Using TCAD Simulation - Shruti Shresta (Slides)

11.2.2015

• Simulation Mismatch: A ChipScope debugging session - Vitali Karasenko (Slides)

21.1.2015

• Journal Club - Exascale Computing - Dr. Johannes Schemmel (Paper)

14.1.2015

• Retrospection - Submission HICANN-DLS - Dr. Andreas Grübl

Seminars 2014

10.12.2014

• Remote Controlling Cadence Simulation Tools from Python - Sebastian Billaudelle (Slides)

22.10.2014

• News from the STiC universe - Tobias Harion

15.10.2014

• First testbeam results of muPix6 - Heiko Augustin

20.8.2014

• Accelerated Neuromorphic Computing Goes Deep Submicron - A 65nm Version of HICANN - Johannes Schemmel

16.7.2014

• Work in progress - Designing Neurons for HICANN DLS - Syed Ahmed Aamir

9.7.2014

• HICANN DLS - Conception and verification plans - Andreas Hartel

4.6.2014

• Constrained random verification with SystemVerilog - Simon Friedmann (Slides)

28.5.2014

• New Results from STiC3 - Tobias Harion (Slides)

21.5.2014

• More results of MuPix6 - Heiko Augustin

14.5.2014

• WrapUp: Virtuoso AMS for Analog Designers - Andreas Hartel

16.4.2014

• Work in progress - SAR ADC - Wei Shen

26.3.2014

• HICANN DLS/Monte Carlo Simulation with optimization - Johannes Schemmel (Slides)

12.3.2014

• First Results MuPix6 - Heiko Augustin (Slides)

26.2.2014

• Experimental Results for a Custom Dual-Port High Speed SRAM - Matthias Hock

19.2.2014

• STiC3 First Power On Results - Tobias Harion
• Short Status Report MUPIX4 - Shruti Shrestha (Slides)

12.2.2014

• First Userresults STiC2 - Patrick Eckert

22.1.2014

• Characterization of a Rail-to-Rail CMOS Output Driver - Syed Ahmed Aamir

Seminars 2013

11.12.2013

• SAR-ADC design - Wei Shen

4.12.2013

• An update on Mu3e pixel Detector - Shruti Shrestha (Slides)

27.11.2013

• MicroBlaze - Tobias Harion

13.11.2013

• AMBA vs. DYI - Simon Friedmann (Slides)

6.11.2013

• Multi-User Mixed-Signal ASIC workflow - Andreas Hartel

30.10.2013

• MuPix: Beam-measurements - Niklaus Berger

2.10.2013

• Structured Data Paths With Encounter - Tobias Harion

25.9.2013

• News about current/voltage cells - Matthias Hock

13.9.2013

• Extraordinary: Submission readiness review of STiC3 - Tobias Harion (Seminar Box II - Room 02.107)

11.9.2013

• SPIKEY5 Submission Readiness/Bug Fix Report - Andreas Grübl

7.8.2013

• STiC3 - Wei Shen, Tobias Harion

17.7.2013

• Short introduction into ACE - Achronix CAD Environment - Markus Dorn

3.7.2013

• First Results Route65 - Matthias Hock

26.6.2013

• Timing characterization of large full-custom blocks - Andreas Hartel

19.6.2013

• New STiC - Tobias Harion

12.6.2013

• Achronix FPGA presentation by Les MacInnes, Achronix

5.6.2013

• CTR measurement of STiC - Huangshan Chen

29.5.2013

• ASIC design for fast timing applications in HEP and Medical Physics - Lluis Freixas, CIEMET

10.4.2013

• Wrap up IDESA Course - Andreas Grübl

13.3.2013

• Analog channel modification for STiC2 - Wei Shen

20.2.2013

• Submission Readiness Review: Route65 - floorplan - Andreas Grübl

13.2.2013

• Submission Readiness Review: Route65 -  digital part - Andreas Hartel

6.2.2013

• Submission Readiness Review: Route65 - analog part - Matthias Hock

30.1.2013

• More STiC2 measurements with LIVE demo - Tobias Harion

23.1.2013

• STiC2: FIB pictures - Tobias Harion
• MMC2: First results - Sebastian Millner
• IDESA course @HD in March, see www.idesa.rl.ac.uk

9.1.2013

• Discussed about new projects for the coming year

Seminars 2012

12.12.2012

• MMC 2.0 measurements report - Sebastian Millner

5.12.2012

• Peak Sensing ADC for SiPM Readout - Wei Shen

28.11.2012

• Dual-Port SRAM optimized for neuronal networks - Matthias Hock

21.11.2012

• Implementation low-pass filter - Lars Sterzenbach

14.11.2012

• 12 bit oscilloscope presentation from Teledyne LeCroy

7.11.2012

• Jitter report STiC - Wei Shen

31.10.2012

• Characterization of ADCs - Alexander Gorel

24.10.2012

• FPGA based testing environment (brICk, flansch, WAF, ... ) - Andreas Hartel

17.10.2012

• Metallic Magnetic Calorimeters - Daniel Hengstler (Slides)

26.9.2012

• Jitter Measurements STiC2.1 - Alejandro Gil Ortiz

19.9.2012

• Analogue Memory - Matthias Hock

22.8.2012

• Analog Digital Converter in AMS 0.35um - Wei Shen

8.8.2012

• More STiC2.1 Measurement Results

1.8.2012

• Random Number Generator - Johannes Schemmel

26.7.2012

• MuPix Mu3e Submission Readiness Review - Niklaus Berger/Ivan Peric

18.7.2012

• STiC2.1 Measurement Results - Tobias Harion

11.7.2012

• HICANN pre-readiness review - Andreas Grübl/Johannes Schemmel

4.7.2012

• MMC readiness review - Sebastian Millner

27.6.2012

• Plasticity processor in HICANN - Simon Friedmann

20.6.2012

• Cell characterization with Altos - Andreas Hartel

6.6.2012

• Lecroy oscilloscope presentation

16.5.2012

• Mu3e detector based on HV-MAPS - Dirk Wiedner (Slides)

25.4.2012

• Wireless transfer: Towards a 60 GHz Multi-Gigabit System-on-Chip - Hans-Kristian Soltveit (Slides)

18.4.2012

• MMC Results - Sebastian Millner, Andreas Hartel

11.4.2012

• Measurement results TSMC 65nm Testchip - Jakob Kunz

4.4.2012

• Design Review STiC2v1 LVS - Tobias Harion

28.3.2012

• Design Review STiC2v1 Overview - Tobias Harion

7.3.2012

• Leakage Current in 65nm Custom SRAM/Capacitive Analog Memory, Part 2 - Matthias Hock

15.2.2012

• Results wafer assembly - Andreas Grübl

8.2.2012

• Simulating chips with brICk - Andreas Hartel

1.2.2012

• A USB-based FPGA platform for Neuromorphic ASICs Part 2/Software stack - Johannes Schemmel

25.1.2012

• Results TSMC 65nm Testchip V2 - Matthias Hock and Simon Friedmann

18.1.2012

• STIC2 results - Tobias Harion

11.1.2012

• Floating Gate Introduction - Sebastian Millner

Seminars 2011

19.12.2011

• Talk about mismatch in a 65nm process - Christian Graf (Slides)

14.12.2011

• A Digital Design for the ATLAS Pixel DCS - Jenny Boek and Lukas Püllen (Slides)

7.12.2011

• Deep submicron noise problems - Wei Shen (Slides)

23.11.2011

• A USB-based FPGA platform for Neuromorphic ASICs Part 1 - Johannes Schemmel

16.11.2011

• KLauS2 measurements - Wei Shen (Slides)

9.11.2011

• Plasticity Processor Version 2 - Simon Friedmann (Slides)

2.11.2011

• After submission MMC report - Sebastian Millner & Andreas Hartl

26.10.2011

• HICANN wafertest - Andreas Grübl

12.10.2011

• LeCroy ArbStudio - H. Fischer (Admess)

28.9.2011

• Submission Readiness Review TC65NM Version 2 - Matthias Hock & Simon Friedmann

21.9.2011

• Submission Readiness Review MMC - MultiCompartmentChip - Sebastian Millner & Andreas Hartel

17.8.2011

• TSMC 65nm Testchip Measurement Results - Matthias Hock

10.8.2011

• Indroduction Current Conveyor/Design Considerations for Multi-Compartment Neurons part 3 - Sebastian Millner

20.7.2011

• Design Considerations for Multi-Compartment Neurons part 2 - Sebastian Millner

13.7.2011

• Presentation STiC 2.0 (TOFPET project) part 2 - Tobias Harion

6.7.2011

• Presentation STiC 2.0 (TOFPET project) part 1 - Wei Shen

29.6.2011

• Design Considerations for Multi-Compartment Neurons part 1 - Sebastian Millner

20.6.2011

• Design Readiness Review - Wei Shen

8.6.2011

• HICANN Testresults/Wafer Readiness Review - Andreas Grübl

1.6.2011

• Europractice course "Power-Aware Design" - Andreas Hartel

18.5.2011

• Mixed-Signal simulation with bi-directional interface elements - Andreas Hartel

20.4.2011

• Cadence Information Day at Tuebingen: "Transaction based modeling and synthesis" - Andreas Grübl

13.4.2011

• Timing Closure in a 65nm process - Andreas Hartel (Slides)

6.4.2011

• "ESD protection circuits - High voltage measurements" -  Marc-Olivier Schwartz (Slides)

30.3.2011

• Readiness review TSMC 65nm Testchip

16.3.2011

• Measurement results from Klaus2

9.3.2011

• Short introduction into Leda, Formality and Encounter Power System (ETS)

2.3.2011

• Discussion about 65nm Testchip for the TSMC process managed by Matthias

16.2.2011

• Talk from Simon about Micro Processor with a Power Architecture (Slides Part 2)

9.2.2011

• Talk about Micro Processor with a Power Architecture - Simon Friedmann (Slides Part 1)

19.1.2011

• Planning testchip in TSMC 65nm

12.1.2011

• "Neujahrsansprache" from Johannes :-)
• Happy New Year

Seminars 2010

15.12.2010

• Bonding talk from Ralf (Slides)

8.12.2010

• "ASIC design flows and verification with waf"

1.12.2010

• Abstract generation von Andreas Gruebl

24.11.2010

• LVS/DRC/ANT Probleme und Loesungen zum KLausV2 Design

27.10.2010

• SystemC/Verilog/VHDL/... Simulation

20.10.2010

• Monte Carlo Simulationen "LIVE"
• TSMC SRAM Macros

13.10.2010

• Chip Design Review - Wei Shen