Schaltungen und Methoden im VLSI Design: Wöchtliches Seminar des ASIC Labors Heidelberg

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Vorträge

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Bisherige Vorträge

26.06.2024

• Overview of 'mneme', an ASIC for memristor crossbar integration tests - Dr. Sebastian Billaudelle (Slides)

05.06.2024

• [Journal] New In-Memory computing concepts from ISSCC 2024 - Dr. Johannes Schemmel (Paper)

28.02.2024

• Physical Design with OpenLane using SKY130 PDK - Gavaskar K (Slides)

21.02.2024

• OpenLANE & SkyWater - Markus Dorn (Slides)

31.01.2024

• Design of a Bandgap Reference Circuit - Arghyadip De (Slides)

29.11.2023

• Periodic poling for nonlinear photonic applications - Philipp Schultzen (Slides)

08.11.2023

• Scalable neuromorphic circuit arrays using PCells - Kaspar Haas (Slides)

04.10.2023

• Calibration and Measurement of an I/O Cell Output Driver - Michael Paping (Slides)

23.08.2023

• [Journal] A compute-in-memory chip based on resistive random-access memory - Dr. Sebastian Billaudelle (Slides)

09.08.2023

• Using Cadence PCELLs for parametrizable analog module - Kaspar Haas (Slides)

19.07.2023

• Design of Integrated Electronics for Driving Photonic Integrated Circuits - Tristan Strahler (Slides)

12.07.2023

• An ASIC, three physicists and an ESD-Gun walk into a lab - Joscha Ilmberger (Slides)

28.06.2023

• [Journal] HERMES Core A - Dr. Johannes Schemmel (Slides)

21.06.2023

• Matrix-vector multiplication using integrated photonic circuits - Jelle Dijkstra & Liam McRae (Slides)

14.06.2023

• Insight CapMems - Philipp Dauer

17.05.2023

• A first proposal for a global routing scheme for the HICANN-Y neuromorphic chip - Dr. Johannes Schemmel (Slides)

10.05.2023

• Problems encountered in the SPADIC chip - Dr. Peter Fischer (Slides)

26.04.2023

• Final circuits for the SAR-CADC - Philipp Dauer (Slides)

19.04.2023

• SS23: ASICs and Ideas - present your planned ASICs and suggestions for our Journal Club - Dr. Johannes Schemmel

08.02.2023

• Submission meshy2: Liberate4meshy - Dr. Andreas Grübl (Slides)

25.01.2023

• Hybrid Photonic-CMOS neuromorphic systems - Dr. Johannes Schemmel (Paper)

26.10.2022

• Novel circuit possibilities with silicon nanowires - Dr. Johannes Schemmel (Paper)

28.09.2022

• Presentation Elmos Semiconductor SE - Dr. Achim Stellberger (Slides)

14.09.2022

• First layout concepts for a novel SAR-ADC for neuromorphic hardware - Philipp Dauer (Slides)

20.07.2022

• Latched Sense Amplifiers: Comparator Design for a SAR-ADC - Philipp Dauer (Slides)

13.07.2022

• A review of classic neuromorphics: translinear circuits and the differential-pair integrator - Dr. Johannes Schemmel (Slides)

06.07.2022

• Ultrafast neural networks for optical communication - Dr. Johannes Schemmel (Slides)

01.06.2022

• Neue Verstärker und ADC-Schaltungen für neuronale Netze - Kamal Abdellatif, Milena Czierlinski, Philipp Dauer (Slides)

23.03.2022

• Mupix11 and beyond - Dr. Heiko Augustin (Slides)

02.03.2022

• Teststand extended: MixedSignal simulations & template repository for analog simulation - Philipp Dauer/Yannik Stradmann (Slides)

16.02.2022

• ADC Design: The Challenges of designing a SAR-ADC - Milena Czierlinski/Philipp Dauer (Slides)

09.02.2022

• Mixed Signal Design Flow for Pixelated ASIC - Dr. Wei Shen (Slides)

15.12.2021

• Sub-nanosecond time measurement using inverter chains - Alexander Schmidt (Slides)

22.09.2021

• Conductance-based synapses for BrainScaleS-2 (and other stuff) - Sebastian Billaudelle (Slides)

15.09.2021

• Automated verification for the upcoming BrainScaleS-2 ASIC - Yannik Stradmann (Slides)

08.09.2021

• How Graph Convolutional Networks bring the power of AI to Electronic Design Automation - Dr. Johannes Schemmel (Paper)

18.08.2021

• Low-power parallel single-ended links for scale-up of neuromorphic hardware - Joscha Ilmberger

11.08.2021

• Discussion/evaluation of results of timing characterization of large mixed-signal blocks with Liberate-AMS - Dr. Andreas Grübl

21.07.2021

• Low-power Capacitor Arrays for Charge Redistribution SAR A/D Converter in 65nm CMOS (Paper)

• Mixed-Signal Computing for Deep Neural Network Inference (Paper)

• A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing (Paper)

14.07.2021

• Presentation different CS-ADC variants - Dr. Johannes Schemmel (Slides)
• Paper presentation: Compact 10b SAR-ADC - Sebastian Billaudelle (Paper)

23.06.2021

• Design Readiness Review SUS65T5 - David Schimansky (Slides)

16.06.2021

• First measurements KLauS6b - Dr. Konrad Briggl (Slides)

09.06.2021

• Literature Seminar: "Memristive and CMOS Devices for Neuromorphic Computing" - Dr. Johannes Schemmel (Paper)

26.05.2021

• Xilinx AI nodes and Versal architecture - Joscha Ilmberger

12.05.2021

• ISSCC 21: in-memory computing - two paper presentations - part 4
  • 16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b of Precision for AI Edge Chips
  • 16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications https://doi.org/10.1109/ISSCC42613.2021.9365766

05.05.2021

• ISSCC 21: in-memory computing - two paper presentations - part 3
  • 16.1 A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices https://doi.org/10.1109/ISSCC42613.2021.9365769
  • 16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing https://doi.org/10.1109/ISSCC42613.2021.9365932

21.04.2021

• ISSCC 21: in-memory computing - two paper presentations - part 2
  • 15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency https://doi.org/10.1109/ISSCC42613.2021.9366045
  • 15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization https://doi.org/10.1109/ISSCC42613.2021.9365989

14.04.2021

• ISSCC 21: in-memory computing - two paper presentations
  • 15.1 A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing https://doi.org/10.1109/ISSCC42613.2021.9365788
  • 15.2 A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating https://doi.org/10.1109/ISSCC42613.2021.9365958

07.04.2021

• Bayesian logic in neuron refractory states - Johannes Weis

20.01.2021

• Keyence Digital Microscope VHX-7000 presentation - Patricia Mohr

16.12.2020

• A Short (Post) Submission Readiness Review "KLauS6b" - Dr. Konrad Briggl

02.12.2020

• Thoughts on conductance-based synaptic input circuits - Sebastian Billaudelle

25.11.2020

• Final Review: Frankensteinboard - Dr. Maurice Güttler

04.11.2020

• HICANN-X: Large macro block timing characterization, first experiences - Dr. Andreas Grübl (Slides)

28.10.2020

• Skillbridge - Tobias Markus (Slides|Github)

21.10.2020

• HICANN-X: Results from testing - the RTL-view part I

30.09.2020

• ASICs for Photon Detection integrating Avalanche Diodes and CMOS Readout - Dr. Peter Fischer (Slides)

23.09.2020

• Final design issues for the BSS-2 mockup-wafer: Project Frankenstein - Dr. Maurice Güttler

16.09.2020

• Run2020: Overview of the latest submissions - Benjamin Weinländer (Slides)

19.08.2020

• EXTOLL News - Tobias Thommes (Slides)

12.08.2020

• Updates on the KLauS6 chip - Dr. Wei Shen (Slides)

22.07.2020

• FPGA design for future HAGEN-mode operation of HICANN-X - Joscha Ilmberger (Slides)

16.07.2020

• Review of first version of new HICANN-X board for single chip platform - Dan Husmann

24.06.2020

• BrainScaleS EXTOLL - A Progress Overview - Tobias Thommes (Slides)

03.06.2020

• Lowest-Energy operation of the HICANN-X ASIC: Testboard development Part IV - Dr. Maurice Güttler, Dan Husmann, Joscha Ilmberger

13.05.2020

• Lowest-Energy operation of the HICANN-X ASIC: Testboard development Part III - Dr. Maurice Güttler, Dan Husmann, Joscha Ilmberger

06.05.2020

• Lowest-Energy operation of the HICANN-X ASIC: Testboard development Part II - Dr. Maurice Güttler, Dan Husmann, Joscha Ilmberger

29.04.2020

• Lowest-Energy operation of the HICANN-X ASIC: Testboard development - Dr. Maurice Güttler, Dan Husmann, Joscha Ilmberger

22.04.2020

• Low-Power Inference Setup for HICANN-X - Joscha Ilmberger (Slides)

15.04.2020

• Wafer-Scale without Wafer : the BrainScaleS FrankenStein Wafer Project - Dr. Maurice Güttler (Slides)

19.02.2020

• Tapeout Review Analog Design Changes HX2 - Sebastian Billaudelle (Slides)

08.01.2020

• Hicann-X-L2comm over JTAG: Serializer-independent Interconnects - Vitali Karasenko (Slides)

Vorträge der letzten Jahre