Teststand extended: MixedSignal simulations & template repository for analog simulation - Philipp Dauer/Yannik Stradmann
(Slides)
16.02.2022
ADC Design: The Challenges of designing a SAR-ADC - Milena Czierlinski/Philipp Dauer
(Slides)
09.02.2022
Mixed Signal Design Flow for Pixelated ASIC - Dr. Wei Shen
(Slides)
15.12.2021
Sub-nanosecond time measurement using inverter chains - Alexander Schmidt
(Slides)
22.09.2021
Conductance-based synapses for BrainScaleS-2 (and other stuff) - Sebastian Billaudelle
(Slides)
15.09.2021
Automated verification for the upcoming BrainScaleS-2 ASIC - Yannik Stradmann (Slides)
08.09.2021
How Graph Convolutional Networks bring the power of AI to Electronic Design Automation - Dr. Johannes Schemmel (Paper)
18.08.2021
Low-power parallel single-ended links for scale-up of neuromorphic hardware - Joscha Ilmberger
11.08.2021
Discussion/evaluation of results of timing characterization of large mixed-signal blocks with Liberate-AMS - Dr. Andreas Grübl
21.07.2021
Low-power Capacitor Arrays for Charge Redistribution SAR A/D Converter in 65nm CMOS (Paper)
Mixed-Signal Computing for Deep Neural Network Inference (Paper)
A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing (Paper)
14.07.2021
Presentation different CS-ADC variants - Dr. Johannes Schemmel (Slides)
Paper presentation: Compact 10b SAR-ADC - Sebastian Billaudelle (Paper)
23.06.2021
Design Readiness Review SUS65T5 - David Schimansky (Slides)
16.06.2021
First measurements KLauS6b - Dr. Konrad Briggl (Slides)
09.06.2021
Literature Seminar: "Memristive and CMOS Devices for Neuromorphic Computing" -
Dr. Johannes Schemmel (Paper)
26.05.2021
Xilinx AI nodes and Versal architecture - Joscha Ilmberger
12.05.2021
ISSCC 21: in-memory computing - two paper presentations - part 4
16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b of Precision for AI Edge Chips
16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications
https://doi.org/10.1109/ISSCC42613.2021.9365766
05.05.2021
ISSCC 21: in-memory computing - two paper presentations - part 3
16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array
Realizing Adaptive Data Converters and Charge-Domain Computing
https://doi.org/10.1109/ISSCC42613.2021.9365932
21.04.2021
ISSCC 21: in-memory computing - two paper presentations - part 2
15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency https://doi.org/10.1109/ISSCC42613.2021.9366045
15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization https://doi.org/10.1109/ISSCC42613.2021.9365989
14.04.2021
ISSCC 21: in-memory computing - two paper presentations
15.2 A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating https://doi.org/10.1109/ISSCC42613.2021.9365958
07.04.2021
Bayesian logic in neuron refractory states - Johannes Weis
20.01.2021
Keyence Digital Microscope VHX-7000 presentation - Patricia Mohr
16.12.2020
A Short (Post) Submission Readiness Review "KLauS6b" - Dr. Konrad Briggl
02.12.2020
Thoughts on conductance-based synaptic input circuits - Sebastian Billaudelle
25.11.2020
Final Review: Frankensteinboard - Dr. Maurice Güttler
04.11.2020
HICANN-X: Large macro block timing characterization, first
experiences - Dr. Andreas Grübl (Slides)
