ASIC laboratory Heidelberg

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 Asic Design Flow Full Custom Design Flow Schematic Entry Analog Simulation Layout Entry Verilog Design Entry Verilog Simulation Verilog Synthesis VHDL Design Entry VHDL Simulation VHDL Synthesis Mixed Signal Simulation Design Rule Check Layout Extraction Post Layout Verilog Netlist Simulation Stream In Stream Out Design Rule Check Layout Extraction Post Layout Parasitic Simulation Post Layout VHDL Netlist Simulation Post Synthesis VHDL Netlist Simulation Mixed Language Simulation Standard Cell Place & Route Post Synthesis Verilog Netlist Simulation Digital Standard Cell Design Flow Post Layout Mixed Language Simulation Layout Versus Schematic Post Layout Mixed Signal Simulation Post Layout Versus Schematic Submission
 
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Last change: 17 May 2001