Verilog Example

The Verilog language is a hardware desription language. The following example will give you a short overview.

Verilog Design Entry

To explain Verilog we want to make a counter. This counter counts only to 2. Open an editor, like nedit, and write the following code in the editor or download the textfile here:

module Ctr3sr(Clk, Reset, Out);
//
// Counts to 3 with synchronous reset
// At every rising edge the if-statment looks at reset and out, if the
// term is fulfilled out will set to 0. Otherwise out will be increased by one.
//
input Clk;         // Clock: rising edge
input Reset;       // synchronous reset
output [1:0] Out;  // counteroutput

reg [1:0] Out;     // register

   always @ (posedge Clk)
     if (Reset || (Out == 2 ))
       Out = 0;
     else
       Out = Out + 1;
endmodule

Additionally we need a testbed Verilog file:

module TestCtr3sr;

reg Clk;           // Clock: rising edge
reg Reset;         // synchronous reset
output [1:0] Out;  // output

   Ctr3sr c(Clk, Reset, Out); // design for test
   initial
   begin
      $dumpfile("TestCtr3sr.vcd"); // command to generate a dumpfile
      $dumpvars(0);                // put all variables in the dumpfile
         Reset = 0;      // reset not activ
         #50 Reset = 1;  // reset activ
         #20 Reset = 0;  // after 1 periode reset not activ
         #200 Reset = 1; // after a while again
         #20 Reset = 0;
      $finish;
   end
   initial // generate clock
   begin
      Clk = 0;
      while(1)
         #10 Clk = !Clk;
   end
endmodule