• Navigation
  • |
  • Content
Ruprecht-Karls-Universität Heidelberg
KIP-Logo
  • News
  • EDA Administration
  • Misc
    • Modules usage
    • Cadence ISCAPE
    • How to print your Cadence layout in A0
    • LVS with a GDS2 file and a verilog netlist
    • Mentor's Calibre in Cadence
    • Commandline DRC/Extract
    • Commandline LVS
    • Mixed Signal Simulation
    • Generate abstract
    • Setup the AMIS HK
    • HSpice MT
    • Usage of the FlexLM utils
    • How Monte Carlo Analysis Works
    • How to use DRACULA DRC
  • Downloads (internal)
  • Chipdatabase
  • Privat (protected)
  • Links
Search
Sitemap | ASIC | ASIC-CC | Contact | Deutsch
Home > Misc > HSpice MT

Running HSpice mit MT option

abaendern des runHspice files:
hspice_mt -mt 2 -i raw/netlist -o netlist.lis > hspice.out
up
© Copyright Universität Heidelberg | Impressum | Datenschutzerklärung