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LVS with a GDS2 file and a verilog netlist

You need a GDS2 file from your design and a verilog netlist.
First we transform the verilog netlist to a spice netlist, because Calibre can only read in spice netlists.
This will be done with the command: v2lvs, which can be found under $MGC_HOME/bin.

v2lvs \
-v verilogfile \
-o spicefile \
-l /UMC/CORECELLS/silicon_ensemble/umcl18u250t2_floorplan.v \
-s library.spi \
-sk -s0 VSS -s1 VDD

in library.spi all corecells are listed

.include /UMC/CORECELLS/spi/ADFULD1.spi
.include /UMC/CORECELLS/spi/ADFULD2.spi