The starter circuit

Helix128-2 features two different resets: first, SufixReset resets all the registers as described in table 5 but, however, leaves the pipeline and multiplexer operation unaffected. Applying a SufixReset signal after power up is not mandatory since the internal registers should wake up atomatically in the 0 state. notReset, on the other hand, only resets the pipeline pointers (described in the following) and the readout multiplexer control circuitry. By activating notReset, which may be done asynchronously, an undefined state in the pipeline or in the multiplexer can be corrected without the need of reprogramming all internal bias registers. For an initial reset we recommend to first perform SufixReset and notReset, then release the SufixReset and load the internal registers as described in section 4.9, and finally release notReset by setting it to +2 V. The adjustment of the pipeline delay according to the desired trigger latency is done by programming the Latency register. To illustrate this feature, we repeat the pipeline operation for convenience (see section 4.1 for a detailed discussion): immediately after releasing the active low notReset (synchronously to the rising edge of Sclk) the write pointer starts walking over the pipeline incremented by Sclk. The pipeline column the write pointer currently points at stores the frontend output voltage at the falling edge of Sclk. The trigger pointer as the second pointer controlling the pipeline points to the pipeline column to be read out if a trigger on TrigIn was given. The start of the pipeline trigger pointer is delayed with respect to the start of the write pointer by the number of Sclk cycles specified in the Latency register thus determining the latency of the pipeline.