Design optimization

With View -> Change Level -> Up you go back to the total view. Select the wecker module and execute Tools -> Design Optimization. In this popup window you can press the OK button.

You will get an error.

This errors occur, because the bcd_dec_lov.v is needed four times in our design. Design Analyser can't assign one module four times. So we have to make four of them. Edit -> Uniquify -> Hierachy checks the topdesign and manifolds the necessary modules.
Before we can optimize the design we have to declare the input and output pads. This is happen in a script called insert_pads.scr, you must modify this script to fullfill your needs. Which can executed by Setup -> Execute Script.... After this script all input- and outputpins have pads. Now we can save the design to a file that can be read from Silicon Ensemble for place and route. File -> Save as ... opens the next screenshot.

After successfully saving the verilog file we can look at various reports which we can create with Analysis -> Report....
For easier use we can create a script file with all necessary commands. If you don't know the name of the command, execute the command via the gui interface and look in the command window (Setup -> Command Window... ) which command it is executed. The script file for this example can you find here.