ASIC laboratory Heidelberg

Content

Tutorials
Cadence
Verilog Example
Verilog XL
Synopsys
Silicon Ensemble

Set Up
Starting GUI
Setting Variables
Import Verilog
Import Power Definition
Floorplan
Place IO
Place Power&Cell
Connect Ring
Route
Batch mode

Dracula, Calibre, ...

Connect power rings

Now it is time to connect the power rings with the pads. Open Route -> Connect Ring... and set Maximun Width from IO Pad to 10.00 and Pin Width from Follow Pins to 1.50. The command takes a few minutes to run. It creates a ring inside th IO rows for IO powere, connects block pins to block rings, connects power stripes to power rings, and connects power rails in standard cell rows. If you see x-shaped markers in your design, they are info markers that mark violations. For this tutorial you can ignore them and continue on.

Connect Power Rings

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Last change: 8 Jun 2001