ASIC laboratory Heidelberg

Content

Tutorials
Cadence
Verilog Example
Verilog XL
Synopsys
Silicon Ensemble

Set Up
Starting GUI
Setting Variables
Import Verilog
Import Power Definition
Floorplan
Place IO
Place Power&Cell
Connect Ring
Route
Batch mode

Dracula, Calibre, ...

Import verilog

The library data for our process can we find under /cad/libs/ams3.20/artist/HK_0.6/LEF/cup/, we need all three files. We import them with File -> Import -> LEF.... Was the import correct you see a No errors found. The database created successfully. in the protocol window. As next we read the timing information File -> Import -> Timing Library... and choose the cup5.0v.gcf file. After this we have all process specified libraries attached and so we can save the design as e.g. libs_loaded. File -> Save As... saves the design.

Import Verilog

The screenshot above shows you the import verilog dialog File -> Import -> Verilog.... You only have to browse to your verilog file, insert the name of the top module and change the verilog output directory to DesignLib.

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Last change: 8 Jun 2001